PhotoChip™ digital camera coprocessor
The PhotoChip digital camera coprocessor is a specialized image signal processor (ISP) and control chip for digital still cameras. It performs a number of programmable functions, including image sensor control, image processing, image JPEG compression and storage to flash media, LCD viewfinder control, and other digital camera functions. The PhotoChip enables high-speed camera operation with excellent image quality.
PhotoAccess (now Shutterfly®)
Product Design and Development Areas
PhotoChip architecture and cores
Contributed to the PhotoChip architecture definition. Designed and developed the following PhotoChip cores:
The Interrupt Controller features 32 interrupt inputs, selectable level or edge triggering for each input, and programmable prioritization.
The Real-Time Counter-Timer features 2 programmable counter-timer channels, each with a programmable count rate and a programmable interrupt output.
Pulse-Width Modulation (PWM) Signal Generator
The Pulse-Width Modulation (PWM) Signal Generator features 10 PWM outputs (configurable to any number of outputs), symmetric dual-edge modulation, programmable frequency on each output, and glitch-free register updating.
General-Purpose Input-Output (GPIO) Unit
The General-Purpose Input-Output (GPIO) Unit features 64 inputs/outputs (configurable to any multiple of 32 inputs/outputs), selectable input level triggering or edge triggering, selectable input switch debouncing, and selectable pin assignment between the GPIO Unit and special-fnction units as required by the application.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) features 4 separate SPI channels (configurable to any number of channels), programmable bit-shift length on each channel, and programmable clock frequency and clock mode on each channel.
The I2C Interface features hardware support for firmware-emulation of the I2C protocol. This relieved the processor from much of the protocol support burden while minimizing the dedicated hardware required for the I2C interface.
Boundary Scan Test Multiplexors
The Boundary Scan Test Multiplexors control multiplexing of test signals to the cores for the ASIC production test.
Coded the cores and associated test benches using Verilog. Simulated using Synopsys VCS and Cadence NC-Verilog on Sun and HP workstations. Assisted in the cores' synthesis to the target device, an NEC cell-based CMOS ASIC, using Synopsys Design Compiler on Sun workstations. Wrote full design specifications and user documentation for each core.
Contributed to the PhotoChip-Camera Emulation Platform design, which used Altera FLEX 10K FPGAs. Synthesized and mapped the PhotoChip cores listed above to the FPGAs using Synopsys FPGA Compiler II and Altera MAX+PLUS II on Sun and PC workstations. Emulated the cores on the emulation platform, validating the cores' operation and enabling pre-ASIC software development. Designed and developed the emulation platform viewfinder LCD interface and video output interface.
Designed and developed the microcode for the PhotoChip programmable timing controller. Wrote microcode for interfacing to a progressive-scan CCD image sensor, an interlaced-scan CCD image sensor, and a CMOS image sensor. Developed a simulation environment including sensor models, using Verilog. Validated the microcode through simulation and emulation of various camera operations.
- "PhotoAccess Announces Availability of PhotoChip™," PhotoAccess.com News, PhotoAccess, June 19, 2000.